1. Field Of The Invention
This invention relates generally to digital processing systems and, more particularly, to a system where there are multiple computers or other devices which communicate among each other over one or more shared data buses. The present invention relates to prevention of allocation errors by an improved mechanism for synchronizing the use of the bus by a multiplicity of such devices.
2. Description Of The Prior Art
In a system in which a plurality of devices are connected such that they may communicate over one or more data buses, there must be some system which determines the priority of use of any given bus by each of the devices. The data to be communicated in such a system may include a code identifying the device as to which data is to be communicated such that when the bus communicates a particular code, particular device is actuated to accept or transmit data and the remaining devices are disabled during the time that particular device is transmitting along the bus. Such an arrangement is economical of intercommunication wiring, however, it does impose the condition that one and only one device may be allowed to communicate data to the bus at any one given instant in time. The procedure for insuring that this condition is met is called bus allocation for time division multiplexing. The devices then communicate by sharing the bus using some sort of time division multiplexing scheme.
The type of system utilizing communication buses in conjunction with a plurality of devices is useful in a wide variety of applications including real-time systems which is industrial process control and military weapons and guidance systems. These systems generally have several computers and interface devices which must pass control information and data back and forth among each other. Thus, they are interconnected with one or more buses via units called bus interface units (BIU.degree.s).
It is customary in designing bus allocation systems to base the design on some demand principle. When a particular device completes its use of the bus, some centralized or distributed apparatus having received signals indicating that various other devices all have data to be communicated to the bus, proceeds according to some demand principle to assign the bus to a particular one of the devices. A typical instance is one in which the various devices are assigned priorities, and the use of the bus is given to them in the order of priority. This is an intricate arrangement and must be made even more intricate if it is desired to assure that the device with the highest priority may not monopolize the bus to prevent lower priority devices from ever using it. In addition, arrangements of this sort are extremely expensive, difficult to design in a fool-proof manner and difficult to simulate and verify. All these factors contribute materially to an ultimate high cost and reduced reliability.
One prior art solution to this dilemma is contained in a patent to Jensen, U.S. Pat. No. 4,017,841, a co-inventor in the present application, and which is assigned to the same assignee as the present application. That invention assigns use of a data bus to the various devices according to a predetermined schedule on a count basis. Each device is connected to the data bus through a bus interface unit (BIU). Each bus interface unit contains a synchronized counter called an address counter and an allocation vector or control schedule memory. The allocation vector has an address pointer which increments through a repeating cycle of counts, each of which is the address of a location in the corresponding allocation vector. The bits and the allocation vectors are set so that for any allocation vector address there is only one bus interface unit which has a logic "one" in the word at that address in its allocation vector memory. Therefore, all allocation vectors in the system are unique. Thus a first device may be enabled once during each counter cycle while a second device may be enabled three times during the cycle and the third device may be enabled twice, all according to the coordinated pre-assigned allocation vector memory distribution.
The mechanism is activated when some unit on the bus sends an allocation synchronization signal. On receipt of that signal all bus interface units increment their address counters, or reset them if the limit of the counter is reached. The selected bit in the allocation vector is examined by each bus interface unit. The bus interface unit which finds a logic "one" can transmit on the bus. All other bus interface units will find a logic "zero" and will therefore not transmit at this time. When the transmitting bus interface unit completes its transmission, which may be a null transmission, it will then send a new allocation synchronization signal and the above procedure will repeat.
While the above system has been successfully used, it is vulnerable to certain types of errors which could occur on the bus or in a bus interface unit. The above scheme depends on maintaining the same value in all address counters and if that value in one bus interface unit ever differs from the counter values in any of the other units, two or more bus interface units could transmit on the bus simultaneously. This phenomenon is known as a "collision" and results in invalid signals which could cause performance degradation or total failure of the bus system. Practical experience has indeed shown this to be a problem. Thus, there has been a need for a bus allocation control mechanism which would successfully synchronize the counts in each of the address counters.